1. Field of the Invention
A present invention relates to a semiconductor memory device and more particularly, to an improvement of an interconnection structure in a memory cell array in an MOS (Metal-Oxide Semiconductor) dynamic RAM (Random Access Memory) or the like.
2. Description of the Prior Art
FIG. 1A is a plan view showing a pattern of a part of a conventional semiconductor memory device having information charge storage capacitance formed on an oblique surface (side surface) of a trench isolation region. FIG. 1B is a cross sectional view taken along a line X-X' of the semiconductor memory device shown in FIG. 1A. In FIGS. 1A and 1B, a trench isolation region 2 for isolating memory cells is formed on a semiconductor substrate SUB. The trench isolation region 2 is formed not to contact a channel region 6 of a transfer transistor constituting the memory cells, but to surround the channel region 6. An n.sup.+ diffusion region 1 constituting one electrode of information charge storage capacitance is formed in a part of a flat portion of the semiconductor substrate SUB and an oblique surface 3 of the side surface of the trench isolation region 2. A thin oxide film 20 is formed on the n.sup.+ diffusion region 1. In addition, an oxide film 21 is formed in the bottom of the trench isolation region 2. A p.sup.+ layer 22 channel stop is formed in the lower portion of the oxide film 21. An opposing electrode 4 formed of first polysilicon is formed on the oxide films 20 and 21. Since the opposing electrode 4 is opposite to the n.sup.+ diffusion region 1 with the oxide film 20 interposed therebetween, the opposing electrode 4 comprises the other electrode of the information charge storage capacitance. Thus, in the semiconductor memory device shown in FIGS. 1A and 1B, information charge storage capacitance is formed not only in the flat portion of the semiconductor substrate SUB but also on the side surface of the trench isolation region 2. Furthermore, a plurality of word lines 5 formed of second polysilicon, a plurality of bit lines 7a, 7b, 7c, 7d, ... formed of third polysilicon or aluminum to intersect with the word lines 5 are formed in the upper portion of the semiconductor substrate SUB. Each of the bit lines is electrically connected to the n.sup.+ diffusion region 1 through an opening 8.
Since the above described semiconductor memory device utilizes the oblique surface portion 3 of the trench isolation region 2 in a peripheral portion of the memory cells as information charge storage capacitance, the area of the flat portion forming the information charge storage capacitance is decreased, operating margin is sufficiently wide even if the chip area is decreased, and information charge storage capacitance capable of holding memory information charges relative to minority carriers injected by radioactive rays such as alpha rays can be ensured. The longer the peripheral length of the memory cell to be utilized is, the shallower the depth of the trench required to obtain the information charge storage capacitance may be.
FIG. 2 is a diagram showing diagrammatically a memory cell array structure when folded bit lines are applied to the semiconductor memory device shown in FIGS. 1A and 1B. A portion enclosed by a dotted line in FIG. 2 substantially corresponds to the semiconductor memory device shown in FIG. 1A. Referring to FIG. 2, a trench isolation region 14 represented by oblique lines is formed to surround a memory cell 9. In addition, adjacent two bit lines out of bit lines 111 to 118 formed to intersect with a plurality of word lines 101 to 108 are connected to an identical sense amplifier 13. Two bit lines connected to the identical sense amplifier 13 constitutes a pair of bit lines. In FIG. 2, the bit lines 111 and 112, 113 and 114, 115 and 116, and 117 and 118 are paired, respectively. One bit line of a pair of bit lines provides contact to the memory cell 9 through an opening 12 (which corresponds to the opening 8 represented diagrammatically in FIG. 1A) arranged every other one memory cell 9. Furthermore, the other bit line out of a pair of bit lines provides contact to the memory cell 9 through the opening 12 arranged to be shifted by one pitch between the above described one bit line and the memory cell 9. Thus, the opening 12 exists with respect to each bit line.
Meanwhile, when the minimum standard of design is applied to the above described semiconductor memory device, an interval between bit lines is defined by a coverage portion surrounding a contact portion of the bit lines (a space provided to surround the opening 8 in FIG. 1A). For example, an interval between the bit lines 7a and 7b is limited by a coverage portion of both bit lines, because the coverage portion surrounding a contact portion of the bit lines is projected inward. Thus, the bit lines can not be arranged at a high density. It is the same with the bit lines 7c and 7d. As a result, capacitance between the bit lines 7a and 7b and capacitance between the bit lines 7b and 7c become unbalanced. In addition, the trench isolation region 14 has a complicated shape such as bricks laid as shown in FIG. 2, so that variation in the process (for example, offset of a mask and variation in depth of a trench) is increased.